The communications industry is rapidly changing to adjust to emerging technologies and ever increasing customer demand. This customer demand for new applications and increased performance of existing applications is driving communications network and system providers to employ networks and systems having greater speed and capacity (e.g., greater bandwidth). In trying to achieve these goals, a common approach taken by many communications providers is to use packet switching technology. Increasingly, public and private communications networks are being built and expanded using various packet technologies, such as Internet Protocol (IP). Note, nothing described or referenced in this document is admitted as prior art to this application unless explicitly so stated.
The use of test and debug instruments embedded in components and boards is becoming more prevalent as device speeds and complexities continue to increase. When implemented on components, they can provide an efficient way of testing and debugging memories, logic and interconnections on boards. If so designed, they can also provide capabilities for measuring jitters, eye diagram, or bit error rates on the high speed lines.
FIG. 1 illustrates a conventional prior art approach for interfacing with embedded testing and debugging instruments distributed across a line card or daughter board via a CPU bus interface and/or via a JTAG interface. Some boards may just provide access via one of these methods, as providing access via both way is an additional expense. However, typically, the different stages of design, testing, manufacturing, and operations do not use the same test equipment, so some require access to the embedded testing instruments via an external CPU, while some require access via a JTAG interface.
First, as shown, the embedded instruments can be accessed via its associated bus (CPUIF) by an external CPU or supervisor connected to the CPU bus controller. Through the CPUIF, a supervisor talks to line cards to bring them up and to run diagnostic routines.
Second, as shown, the embedded instruments can be accessed via a conventional IEEE 1149.1 (JTAG) interface. IEEE 1149.1 has been adopted industry wide for testing PCB interconnections on board. Beyond the main objective, it is used for interfacing the embedded test and debug instrument on boards or ASICs. The JTAG interface is the standard interface in board manufacturing flow from ICT (In-Circuit Test) to debug station. A JTAG interface is typically mandatory for using embedded instruments during manufacturing. Note, a variant of this approach is not to provide a centralized accessible JTAG TAP that daisy chains to all ASICs, but rather to use a separate physical connection to each JTAG TAP of each ASIC, which can be problematic if it is desired to control embedded testing instruments in multiple ASICs at the same time. This daisy-chain approach requires a lot of expense and could be a source of board connectivity routing errors and complications that must overcome. This approach adds design complexity as all the registers required to run embedded instruments must be identified, and test data registers must be allocated with access to these registers provided via the JTAG TAP. Also, generating the appropriate patterns to control the embedded instruments is quite complex, and these patterns depend on the implemented JTAG chain through the components, therefore, these patterns are different for each implementation.
Engineers have desired for a long time a better approach, but have in the past have had to settle for JTAG accessing the embedded testing equipment either through the daisy-chain approach or via direct JTAG connections to each ASIC.